| Role | Name | Date | |------|------|------| | Designer | [Name] | 2026-04-14 | | Reviewer | [Name] | 2026-04-15 |
| Test Case | Description | Expected Output | Simulation Result | Pass/Fail | |-----------|-------------|----------------|-------------------|------------| | Reset | Assert reset for 10 ns | All outputs zero | Matched | Pass | | Normal Operation | Input = 0xA5 | Output = 0xA5 after 2 cycles | Waveform verified | Pass | | Overflow | Input = 0xFF + 1 | Overflow flag = 1 | Flag asserted | Pass | vivado design